1. Field of the Invention
The present invention relates in general to programmable delay circuits and in particular to a programmable delay circuit for selectively providing any one of a set of delays, wherein each delay is independently calibratable.
2. Description of Related Art
A typical prior art programmable delay circuit includes a tapped delay line and a multiplexer. The delay line is formed by a set of delay stages connected in series for successively delaying an INPUT signal. Each delay stage may, for example, be a simple logic gate which passes an input signal to its output with a delay that depends on the response characteristics of the logic gate. With the output of each delay stage constituting a separate "tap" of the delay line, the INPUT signal appears at each tap in succession as the signal pulse traverses the delay line. The delay line taps are connected to separate inputs of the multiplexer which produces the delay circuit output. The programmable delay circuit is programmed to provide a desired delay simply by supplying input control data to the multiplexer so that it passes a selected one of its input delay line taps to its output. The delay of the programmable delay circuit is the sum of the delays of all delay line elements through which the input pulse passes enroute to the selected tap, along with the time required for the input pulse to travel though the multiplexer itself.
A "linear" programmable delay circuit provides a delay that is a selected multiple of a desired unit delay. If all elements of a delay line had the same unit delay, then the total delay provided by the programmable delay circuit would be a linear function of the number of delay elements the input signal passes through enroute to the selected tap. However even though delay elements may be formed by similar logic gates, "similar" logic gates typically not provide exactly the same delay because, due to integrated circuit process variations, the gates are not exactly similar, even when implemented on the same integrated circuit.
The article entitled "CMOS Programmable Delay Vernier" by Masaharu Goto et al, published in the United States of America in October 1994 in the Hewlett-Packard Journal, describes a system for correcting non-linear characteristics in a programmable delay circuit of the type employing a multiplexer to select a tap of a tapped delay line. This article describes each element of the tapped delay line as being formed by two inverter stages connected in series with a variable capacitor coupling the output of the first inverter stage to ground. The capacitance provided by the capacitor within each stage is selected by data stored in a separate register for each stage. The delay of each element is a function of the delays of the two inverter stages and the selected amount of capacitance. The Goto et al article teaches that to provide for linear characteristics one can adjust the delay provided by each delay element by adjusting the capacitance for that element so that the delay element provides a desired unit delay. One drawback to this system is that a delay line having many delay elements requires many capacitors and registers.